The present invention relates to the fabrication of junction diodes, particularly to a process for forming thin-film silicon junction diodes on a thin metal film, and more particularly to direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory cells, such as used for high-performance, non-volatile memory.
Magnetic random access memory (MRAM) using giant magneto-resistance (GMR) materials and spin-dependent tunneling (MTJs) has been developed for high-performance, non-volatile memory. Such memory cells have significant advantage over previous state-of-the-art in that they are current-perpendicular-to-plane (CPP) devices, that is, sense current flows perpendicularly from word-to-bit line through the memory, whereas, in previous configurations, sense current flowed in the plane (CIP) of the memory element. The CPP configuration results in a number of advantages including minimum size cell and ease of dimensional scaling with semiconductor feature sizes. The basic magnetic storage element in a CPP MRAM cell consists of two magnetic multilayers (GMR films) separated by a thin insulator (for instance Al2O3). The magnetization moments of the two films may be either parallel or anti-parallel, such alignment defining either a logic “1” or “0” for the cell. These states are written by passing a write current through the word and bit line. This current, which should not flow through the cell, creates a magnetic field that switches the direction of the moment of one of the GMR layers. For the read process, a sense current is passed perpendicular through the cell, generating a voltage from the magneto-resistance of the cell. Thus, the magneto-resistance of the cell contains the information on the state of that cell.
For fabrication of a memory from these cells, the cells are placed between word and bit line intersections, forming an array of n×n cells. To write or read a cell, ni, the word and bit lines whose intersection occurs at ni are activated. However, since the cells are essentially resistors, problems arise in read and write sensitivity as a result of shunt currents passing through cells other than ni. Such problems are eliminated by placing an electronic switch between the word and bit lines in series with each magnetic cell. Such a device can be a diode or transistor whose impedance is controlled by differences between the word and bit line voltages.
Accordingly, there is a need for providing this electronic switch between word and bit lines in series with the magnetic cell. There is also a need for developing a fabrication process allowing the construction of a silicon diode or transistor directly onto a metal word or bit line that can be manufactured. There is also a need for this process to be low temperature, so as to not affect the metal word or bit lines or underlying or adjacent Si electronics.
The present invention provides a solution to the above needs wherein the needs are met by direct vertical integration of a diode or transistor (voltage controlled switch) with the MTJ stack between the word and bit lines. This process is carried out without thermal damage to the underlying Complementary Metal Oxide Semiconductor Integrated Circuit (CMOS IC) circuitry by using appropriate low temperature deposition steps in conjunction with a pulsed energy source for melting, recrystallizing, and doping the deposited amorphous Si films. This allows formation of the p-n junction or TFT directly onto the surface of the word/bit lines.